As the size of semiconductor devices decreases, various problems arise. Particularly, the control of device characteristics, such as transistors, becomes more difficult as the feature size of devices goes below one micron. In order to control device characteristics, it is important to control processes such as ion implantation and etching during the fabrication of these devices. One technique for controlling such processes involves the use of permanent spacers and disposable spacers. For example, spacers may be utilized to offset the implantation of ions relative to another structural feature of the device or offset an etch of a material relative to a different region of the device being fabricated.
For illustration, in submicron CMOS technologies, PMOS devices typically show a short channel behavior, which is partly caused by lateral diffusion of a dopant, such as boron, into the gate channel of the PMOS device after implant of active areas of the PMOS device. Although, typically, a permanent spacer is utilized for offset of the ion implant from the gate edge in order to widen the gate channel, the spacer width for the PMOS device is usually determined based on the spacer width necessary to create an adequately sized gate channel for NMOS devices fabricated at the same time. Such a spacer width is typically too small to account for the larger diffusion of, for example, boron, into the gate channel of the PMOS device, as opposed to the diffusion of arsenic into the gate channel of an NMOS device. As such, the gate channel is usually shorter than desired for the PMOS device.
Typically, the gate has a large stack height that permits the formation of an additional spacer for PMOS devices to offset the ion implant (i.e., boron) further from the gate so as to allow for greater lateral diffusion in the underlying substrate. Various spacer materials are available; however, use of such spacers creates other problems. For example, a polysilicon spacer could be utilized to offset the implant. However, the removal of the polysilicon spacer after the implant is performed, is difficult to achieve without leaving stringers or over etching into the poly gate or substrate. Further, for example, a silicon nitride spacer if used creates too small of a permanent gap between narrowly spaced gates (i.e., wordlines) for the formation of a bit line contact therebetween. Further, for example, an oxide spacer could also be utilized. However, the removal of the oxide spacer would lead to a loss of field oxide.
An additional illustration of controlling semiconductor device characteristics through the use of fabrication techniques includes the use of an ion implantation in a local oxidation of silicon (LOCOS) process to optimize isolation between the active areas of the devices fabricated. Such a field implant during the LOCOS process is commonly referred to as a channel stop implant. However, the channel stop implant introduces a dopant diffusion encroachment problem wherein the dopant laterally diffuses into active area/channel regions formed by the LOCOS process. The overall effect is that the width of the channel/electrical active area being formed by the LOCOS process is undesirably reduced.
More particularly, a silicon nitride mask is typically utilized as the oxidation mask for the LOCOS process. Although spacers have been formed relative to the silicon nitride mask for offsetting the channel stop implant, such spacers also cause problems as in the case of polysilicon, silicon nitride, or oxide spacers. Such problems include changing the shape of the field oxide grown, removal of portions of the field oxide during etching of the spacer such as with use of an oxide spacer, or, for example, some of the materials may not be selectively etchable relative to the oxidation mask. For example, if a silicon nitride spacer is utilized with a silicon nitride oxidation mask, selective removal would not be possible.
For the above reasons, there is a need in the art for new disposable spacers, in addition to methods of forming and using such spacers to provide desirable semiconductor device characteristics. The present invention, as described below, overcomes the problems described above and other problems which will become apparent to one skilled in the art from the description below.